The present application relates to methods of forming a semiconductor device, and more particularly to methods of forming gate-all-around transistors which include at least one germanium-containing nanowire and/or at least one III-V compound semiconductor nanowire.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
Gate-all-around semiconductor nanowire transistors are a candidate for future complementary metal oxide semiconductor (CMOS) generations due to the excellent electrostatics and immunity to short channel effects. High-mobility semiconductor materials such as germanium (both high hole and electron mobility) and III-V compound semiconductor materials (mostly high electron mobility, but some high hole mobility) are needed for high performance CMOS devices. Thus, combining a gate-all-around semiconductor nanowire transistor architecture and germanium and/or III-V compound semiconductor materials are beneficial for both ultimate scalability and high performance.